1. Field of the Invention
The present invention relates to a test pattern evaluation method and a test pattern evaluation device for a reliability test of a semiconductor integrated circuit.
2. Description of the Related Art
Conventionally, in order to ship a highly reliable semiconductor integrated circuit device, various kinds of reliability tests are performed for the semiconductor integrated circuit device before shipment. The reliability tests include an endurance test for a gate oxide film of a transistor constituting a semiconductor integrated circuit. More specifically, in the endurance test for the gate oxide film of the transistor, while an endurance testing power supply voltage higher than a rated voltage is applied to a power supply terminal of the semiconductor integrated circuit in a high-temperature environment, depending on a process, characteristics and the like, an input signal produced based on a test pattern for testing endurance of the gate oxide film of the transistor is inputted to an input terminal of the semiconductor integrated circuit. Thus, in the endurance test for the gate oxide film of the transistor, the endurance testing voltage is applied to the gate oxide film of the transistor to be tested for a time required for the reliability test.
Meanwhile, in the reliability test for the gate oxide film of the transistor, in order to improve the precision of the reliability test, it is necessary to apply an appropriate endurance testing voltage to all the transistors constituting the semiconductor integrated circuit for an appropriate period of time. When the endurance testing voltage and the voltage application time for the transistor are varied, there is a possibility that the precision of the reliability test is lowered. Therefore, it is necessary to produce a reliability testing test pattern in which an endurance testing voltage can be applied to all the transistors constituting the semiconductor integrated circuit for an appropriate time.
In general, when the semiconductor integrated circuit is large in size especially, since it is difficult to apply the endurance testing voltage to all the transistors constituting the semiconductor integrated circuit for the appropriate time in one reliability testing test pattern, a plurality of reliability testing test patterns are used in some cases. Alternatively, as the size of the semiconductor integrated circuit becomes large, a length of one reliability testing test pattern tends to be increased. However, when the number of reliability testing test patterns is increased or when the length of the reliability testing test pattern is increased, a testing time of the endurance test is increased considerably. Therefore, it is required to produce a high-precision reliability testing test pattern, reduce the number of reliability testing test patterns, and reduce the testing time of the endurance test, and a technique to appropriately evaluate the precision of the reliability testing test pattern is required.
A technique for evaluating the reliability testing test pattern includes a test pattern evaluating technique in which with a SPICE (Simulation Program with Integrated Circuit Emphasis) netlist of a semiconductor integrated circuit and the reliability testing test pattern, SPICE simulation is performed at a transistor level, a transistor to which an endurance testing voltage is applied for an appropriate time is extracted as an activation transistor, and an activation rate (stress activation rate) of the transistor in the whole semiconductor integrated circuit is calculated from a ratio of the activation transistors to all the transistors in the semiconductor integrated circuit (refer to Japanese Patent Application Laid-Open No. 2006-118880 (hereinafter referred to as the patent document 1), for example).
The evaluation technique of the test pattern disclosed in the patent document 1 will be briefly described with reference to FIGS. 18 and 19.
First, a constitution of an inspection device used in the test pattern evaluation technique disclosed in the patent document 1 will be described with reference to FIG. 18. Here, FIG. 18 shows one example of the inspection device for a semiconductor integrated circuit, especially, a schematic constitution example of a part regarding the SPICE simulation.
As shown in FIG. 18, an inspection device 1000 comprises a CPU (Central Processing Unit) 1010 controlling various kinds of functions of the inspection device 1000, a SPICE simulation program 1021 composed of processing procedures of the SPICE simulation, a HDD (Hard Disk Drive) 1020 storing a SPICE netlist 1022 of the semiconductor integrated circuit, a reliable testing test pattern 1023 and the like, a RAM (Random Access memory) 1030 as a temporal memory device composed of a flash memory and the like, an operation unit 1040 comprising external input devices such as a keyboard and a mouse from which setting and operation request of the SPICE simulation can be inputted, a display unit 1050 comprising a device such as a display capable of displaying a result of the SPICE simulation and the like, and a communication interface 1060 for data communication with another device on a LAN (Local Area network).
The inspection device 1000 carries out a reliability test for the semiconductor integrated circuit in which the CPU 1010 carries out the SPICE simulation program 1021 using the SPICE netlist 1022 and the reliability testing test pattern 1023 stored in the HDD 1020, based on an execution instruction for the SPICE simulation from the operation unit 1040.
Next, the execution procedures of the test pattern evaluation technique described in the patent document 1 will be described with reference to FIG. 19. Here, FIG. 19 shows the process procedures of the evaluation technique of the reliability testing test pattern according to the conventional technique.
When the CPU 1010 of the inspection device 1000 receives the execution request for the SPICE simulation from the operation unit 1040, it acquires the designated SPICE netlist 1022 and reliability testing test pattern 1023 from the HDD 1020, and executes the SPICE simulation program 1021 stored in the HDD 1020 to start the simulation at a transistor level (step #1001).
The CPU 1010 extracts transistor names of all the transistors and each node of each transistor from the SPICE netlist 1022 to form a transistor list (step #1002). Furthermore, the CPU 1010 executes the SPICE simulation or uses a log of the SPICE simulation to acquire a voltage change of each node of each transistor (step #1003).
After the CPU 1010 acquires the results of the SPICE simulation for all the transistors (“YES” branch in step #1004), it acquires a stress application time for each transistor in which an endurance testing voltage is applied to the gate oxide film of the transistor from the result of the SPICE simulation (step #1005), and calculates a ratio of the stress application time to total SPICE simulation time (stress application rate) (step #1006).
After the CPU 1010 calculates the stress application rates of all the transistors (“YES” branch in step #1007), the CPU 1010 acquires the number of transistors whose value of the stress application rate is not less than a certain value (step #1008), and calculates a ratio of such transistor number to the total transistor number in the semiconductor integrated circuit, as a transistor activation rate (step #1009) and outputs it to the display unit 1050. Finally, the test pattern is evaluated using the transistor activation rate as an evaluation index of the reliability testing test pattern 1023.
In addition, although the transistor activation rate showing the application state of the endurance testing voltage to the gate oxide film of the transistor is used as the evaluation index of the test pattern, in the above evaluation technique of the test pattern, as another evaluation technique of the test pattern, a toggle rate is used as the evaluation index of the test pattern, for example (refer to Japanese Patent Application Laid-Open No. 2003-197746 (hereinafter referred to as the patent document 2), for example).
The toggle rate is an activation rate of a bus connecting an output terminal of a certain cell to an input terminal of another cell, in a semiconductor integrated circuit; it is shown by a ratio of the bus number capable of changing a logic value to “0” and “1” to the total bus number. The toggle rate is used in a logic circuit that is designed using a library made based on a standard cell composed of about several to several tens of transistors especially.
However, according to the evaluation technique of the test pattern disclosed in the patent document 1, since the voltage characteristics are analyzed at the transistor level by the SPICE simulation, the simulation time is considerably long. Especially, when transient analysis of the SPICE is used to perform the simulation with high accuracy, the simulation time is enormously long and the problem is that the SPICE simulation cannot be completed in a realistic time. Furthermore, as the semiconductor integrated circuit becomes large recently, the SPICE simulation time is increased accordingly, so that it becomes difficult to evaluate the reliability testing test pattern using the SPICE simulation like the evaluation technique of the test pattern disclosed in the patent document 1. Thus, an evaluation technique of the test pattern is required to be capable of acquiring a transistor activation rate using a simulation at a gate level (cell unit) in which a process can be completed in a realistic time comparatively even when the semiconductor integrated circuit becomes large.
In addition, according to the evaluation technique of the test pattern disclosed in the patent document 2, although the toggle rate showing the activation rate of the bus is used as the evaluation index of the test pattern, it is necessary to apply a logic value to the bus node in the semiconductor integrated circuit comprehensively in order to improve the toggle rate. Meanwhile, in the reliability test for the gate oxide film of the transistor, the voltage between the terminals of the transistor only has to be in a test voltage application state for a time required for the reliability test. That is, even when the test pattern has a high toggle rate, the evaluation of the reliability test for the gate oxide film of the transistor is not always high. The toggle rate, fault coverage and the like are not always suitable for the evaluation index of the reliability testing test pattern for the gate oxide film of the transistor.